Contacts are typically vertical metal interconnect structures formed in an integrated circuit that connect the diffusion regions and gate electrodes of a semiconductor device to the first layer of interconnect. Individual semiconductor devices formed in a semiconductor substrate are usually electrically coupled to each other through contacts in order to form functional integrated circuits. The desired characteristics of a contact include a minimum contact resistance, ease of fabrication, and good reliability.
FIG. 1 shows a cross sectional view of a semiconductor device employing the conventional self-aligned silicide, tungsten plug contact configuration. In forming this prior art contact structure, after the creation of transistors is complete, a silicide layer 5 is deposited and patterned atop the source/drain and gate regions of MOS transistors, such as s1, d1, g1 of MOS transistor m1, s2, d2, g2 of MOS transistor m2 and g3 of another MOS transistor (not shown). Silicide layer 5 is used to reduce the resistance of the source/drain diffusion regions in the substrate 2 and the gate electrodes. A dielectric layer (ILD) is then typically formed atop the substrate 2 and polished through a planarization process to form a flat surface. Photoresist is generally deposited and patterned, and a dry etch process is usually employed to cut holes through the ILD where contacts are desired. Chemical vapor deposition (CVD) tungsten may then be used to fill in the contact holes. Another planarization process may be employed to remove tungsten residues on the substrate and create a flat substrate surface for subsequent processing steps. As shown in FIG. 1, contacts thus formed may include regular, square-shaped contacts 8 landing on an area in the source/region or gate region of MOS transistor m1 and m2. The contacts may also include rectangular-shaped contact 10, having a much larger size than regular contact 8. Contact 10 rides across two conductive regions on a substrate, such as the source region s2 of transistor m2 and the gate electrode g3 of another MOS transistor (not shown), having a configuration generally referred to as a butted contact (BTC). BTC contact 10 abuts two conductive regions and can significantly reduce the number of contacts needed. In general, BTC contacts are used in making electrical connections to a die area where high device density is desired, such as an embedded SRAM and DRAM cell area, thus, reducing the die area and enhancing device reliability.
FIG. 2 illustrates the layout view of the device in FIG. 1 with prior art contacts added. In FIG. 2, two contacts 8 having a minimum design-rule size are used in each of the source region s1 and drain region d1 of the transistor m1. As recognized in the art, a contact with a minimum design rule size exhibits a high overall yield and reliability while occupying the smallest possible silicon area. Contact 8 has a square-shape with an edge dimension of “λ.” Two square-shaped contacts 8 are connected to the drain region d2 of the transistor m2. Two BTC contacts 10 are used to couple the source region s2 of m2 and the gate electrode g3 of another MOS transistor (not shown).
However, as transistor dimensions continue to scale down in advanced processing technology, this and other prior art contact structures begin to limit device performance in various ways. First, further feature size scaling can lead to contacts with very large aspect ratio (i.e., contact depth versus contact width), close to 10:1 under some circumstances. Cutting contact openings having an aspect ratio of this level will typically take a much longer time, compared with the dry etch process used in forming the contact openings in the prior art. A detrimental effect known as “striation” may also occur on the surface region between adjacent contact holes due to severe photoresist losses on the edges of the contact openings during the long plasma etch process. “Striation” causes electrical shorting between adjacent contacts and may cause severe device yield loss. This problem is compounded by the increased contact opening density on a wafer surface processed using advanced technology.
Second, in forming a contact, a tapered contact opening profile is usually preferred to provide desired step coverage by the metal that is filled into it. However, a tapered contact opening with a very large aspect ratio may result in a substantially reduced contact landing area on the source/drain region and gate electrode. This may, in turn, lead to a substantial increase in contact resistance and deteriorated device performance.
Third, the contact openings are aligned with the source/drain region and gate electrode through a separate photolithography step. Due to the shrunken device feature sizes, the margin for a misalignment between the contact openings and the source/drain region and gate electrode is significantly reduced in advanced technology. A reduced margin for misalignment may cause substantial device yield loss or create serious device reliability concerns, especially in a butted contact area, where a misalignment may easily cause a complete disconnection to a diffusion region or a gate electrode.
In view of these and other problems in the prior art contact structures used in an existing semiconductor device, there is a need for improved contact structures and methods of forming the same in order to cope with the continuous trend of device scaling and maintain the desired characteristics, such as low contact resistance, ease of making and highly reliable.